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1 of 50 semtech gv7700 final data sheet rev.7 pds-060377 december 2015 gv7700 hd-vlc? transmitter www.semtech.com key features ? serial digital video transmitter for hd and 3g video surveillance and hdcctv applications ? quad rate operation: 270mb/s, 540mb/s, 1.485gb/s, and 2.97gb/s ? supports hdcctv 1.0, hd-sdi (st 292), 3g-sdi (st 424), and sd-sdi (st 259) 1 ? integrated high definition visually lossless codec (hd-vlc?) for extended cable reach: ? hd over 550m of belden 543945 cctv coax at 270mb/s ? full hd over 400m of belden 543945 cctv coax at 540mb/s ? hd over 150m of cat-5e/6 utp cable at 270mb/s ? configurable 50/75 ? cable driver output, for both coaxial and twisted pair cable transmission ? integrated audio embedder with support for up to 4 channels of i 2 s serial digital audio at 32khz, 44.1khz and 48khz sample rates ? downstream ancillary data insertion ? supports both 720p and 1080p hd formats: ? full hd: 1080p50/59.94/60fps ? hd: 1080p25/29.97/30fps ? hd: 720p25/29.97/30/50/59.94/60fps ? support for both 8/10-bit and 16/20-bit bt.1120 compliant video interfaces, with embedded trs or external hvf timing ? 4-wire gennum serial peripheral interface (gspi 2.0) for external host command and control ? dedicated jtag test interface ? 1.8v core power supply and 1.8v or 3.3v digital i/o supply ? small-footprint 84-pin dual-row qfn (7mm x 7mm) ? low power operation, typically 180mw ? wide operating temperature range: -20c to + 85c ? pb - free and rohs compliant applications ? hd/3g security cameras ? industrial cameras ? hd-sdi, 3g-sdi, and hdcctv peripherals ? media converters ? video multiplexers description the gv7700 is a serial digital video transmitter for high definition component video. with integrated cable driving technology, the gv7700 is capable of transmitting compressed video at 270mb/s or 540mb/s, or uncompressed video at 1.485gb/s or 2.97gb/s, over 75 ? coaxial cable, or differentially over 100 ? twisted pair cable. the gv7700 integrates the high definition visually lossless codec (hd-vlc?) technology, which has been developed specifically to reduce the tran smission data rate of hd video over both coaxial and un shielded twisted pair (utp) cable. this is achieved by encoding the hd video, normally transmitted at a serial data ra te of 1.485gb/s, to the same rate as standard definition (sd) video, at 270mb/s serial data rate. 550m belden 543945 coaxial cable gv7700 transmitter hd-vlc? camera hd-vlc? dvr hd video codec hdmi output hd-sdi or hd-vlc cameras gv7704 quad receiver image signal processor hd sensor gv7700 transmitter power sink power source rs422 rs422 in1 in2 in3 in4 150m cat-5e/6 cable hd-vlc? dvr hd-vlc? camera hdd storage gv7704 quad receiver coaxial cable application utp cable application hd at 270mb/s hd at 270mb/s
gv7700 final data sheet rev.7 pds-060377 december 2015 2 of 50 semtech www.semtech.com at 270mb/s, the effect of cable loss is greatly reduced, resulting in much longer cable transmission. for 75 ? coaxial cable, hd-vlc allows a 1.485gb/s hd signal to be transmitted up to 3x the normal reach. in typical video over coaxial installations, when pa ired with semtechs gv7704 hd-vlc receiver, cable distances over 550m are possible. similarly, a 2.97gb/s 3g signal can be transmitted at 540mb/s using hd-vlc. the gv7700 can also be config ured to transmit hd and 3g video over utp cable, such as cat-5e and cat-6 cable, when hd-vlc encoded at 270mb/s and 540mb/s, respectively. the device supports both 8-bit and 10-bit per pixel ycbcr 4:2:2 bt.1120 component digital video. a configurable 20-bit or 10-bit wide parallel digital video input bus is provided, with associated pixel clock and timing signal inputs. the gv7700 supports direct interfacing of hd video formats conforming to itu-r bt.709 and bt.1120-6 for 1125-line formats, and smpte st 296 for 750-line formats. the gv7700 features an audio embedding core, which supports up to 4 channels of i 2 s serial digital audio within the ancillary data space of the video data stream. the audio embedding core supports 32khz, 44.1khz, and 48khz sample rates. the gv7700 supports the insertion of ancillary data into the horizontal blanking of the video data stream. user data can be programmed via the gspi, allowing downstream communication from the video source to sink device. the ancillary data packing format is compliant with hdcctv 2.0 communications protocol. packaged in a space-saving 84-pin dual-row qfn, the gv7700 is ideal for single pcb security cameras, where high-density component placement is required. typically requiring only 180mw of power, the device does not require any special heat sinking or air flow, reducing the over-cost of hd security camera designs. 1 frame structure with encoded hd only. does not support sd/d1 video . functional block diagram gv7700 functional block diagram din_[19:0] hin 20 formatter gspi sdin cs sclk sdout sdo sdo hd-vlc encoder xo audio / ancilliary insertion hdvlc _en digital control vin fin pclk output formatter bit20_bit10 detect_trs trst tdi tms tck tdo wclk aclk ain _1_2 ain _3_4 test pattern generator pll tx clock xtal xtal_out digital clocks p2s reset audio_en div_1001 xtal54_sel sdo_50_en pclk rbias jtag programming xtal_en xtal
gv7700 final data sheet rev.7 pds-060377 december 2015 3 of 50 semtech www.semtech.com revision history contents 1. pin out..................................................................................................................... ............................................5 1.1 gv7700 pin assignment ..................................................................................................... ..............5 1.2 pin descriptions .......................................................................................................... ........................6 2. electrical characteristics.................................................................................................. ........................... 10 2.1 absolute maximum ratings .................................................................................................. ...... 10 2.2 dc electrical characteristics ............................................................................................. ........... 10 2.3 ac electrical characteristics ............................................................................................. ............ 11 3. input/output circuits....................................................................................................... ........................... 13 4. detailed description........................................................................................................ ............................ 14 4.1 functional overview ....................................................................................................... ............... 14 4.2 parallel video data inputs din_[19:0] ..................................................................................... .15 4.2.1 parallel input in video mode........................................................................................... 15 4.3 video processing .......................................................................................................... ................... 21 4.3.1 h:v:f timing ............................................................................................................. ............. 21 4.4 hd-vlc? encoder ........................................................................................................... ................. 22 4.5 stream id packet insertion ................................................................................................ ........... 23 4.6 audio embedding ........................................................................................................... ................ 25 4.6.1 serial audio data inputs ................................................................................................. .. 25 4.6.2 serial i2s audio data format .......................................................................................... 26 version eco pcn date description 7 029012 december 2015 updated values in table 2-3: ac electrical characteristics . 6 028866 december 2015 updated to final data sheet from preliminary data sheet. 5 027517 september 2015 removed proprietary and confidential from footer. updated table 1-1 , table 2-3 , section 4.4 , section 4.11 , section 4.14 , figure 4-18 , and figure 6-1 . added figure 6-2 . 4 027026 july 2015 updated cable reach values. updated table 2-2 and table 2-3 . 3 025836 may 2015 updated to preliminary data sheet from draft data sheet 2 025126 april 2015 updated gv7700 functional block diagram , figure 1-1 , figure 6-1 . updated table 2-2 and table 2-3 . various updates throughout document. 1 024223 february 2015 updated table 1-1 , table 2-2 , section 4.1 0 020611 august 2014 new document
gv7700 final data sheet rev.7 pds-060377 december 2015 4 of 50 semtech www.semtech.com 4.6.3 audio mute............................................................................................................... ............. 26 4.6.4 ecc error detection and correction............................................................................. 26 4.7 ancillary data insertion .................................................................................................. ............... 27 4.8 additional processing functions ........................................................................................... .... 29 4.8.1 test pattern generation.................................................................................................. .. 29 4.8.2 trs generation and insertion ......................................................................................... 32 4.8.3 hd line number calc ulation and insertion............................................................... 32 4.8.4 line based crc gene ration and insertion.................................................................. 32 4.8.5 illegal code re-mapping .................................................................................................. 32 4.9 parallel to serial conversion ............................................................................................. ........... 32 4.10 pll ...................................................................................................................... ................................ 33 4.10.1 frequency reference..................................................................................................... .. 33 4.11 serial data output ....................................................................................................... ................. 34 4.11.1 output signal interface levels..................................................................................... 35 4.11.2 serial data output signal............................................................................................... 35 4.12 gspi host interface ...................................................................................................... ................. 35 4.12.1 cs pin........................................................................................................................... .......... 35 4.12.2 sdin pin................................................................................................................ ................ 36 4.12.3 sdout pin ............................................................................................................... ............ 36 4.12.4 sclk pin................................................................................................................ ................ 36 4.12.5 command word description........................................................................................ 36 4.12.6 data word description ................................................................................................... 37 4.12.7 gspi transaction timing ................................................................................................ 3 8 4.12.8 single read/write access............................................................................................... 3 9 4.12.9 auto-increment read/write access ........................................................................... 40 4.13 jtag ..................................................................................................................... .............................. 40 4.14 power supply and reset timing ............................................................................................ .. 41 5. register map................................................................................................................ ................................... 42 6. typical application circuit ................................................................................................. ....................... 45 6.1 power supply decoupling and filtering ................................................................................. 46 7. packaging information ....................................................................................................... ........................ 47 7.1 package dimensions ........................................................................................................ .............. 47 7.2 recommended pcb footprint ................................................................................................. ... 48 7.3 marking diagram ........................................................................................................... .................. 48 7.4 solder reflow profile ..................................................................................................... ................. 49 7.5 packaging data ............................................................................................................ .................... 49 7.6 ordering information ...................................................................................................... ............... 49
gv7700 final data sheet rev.7 pds-060377 december 2015 5 of 50 semtech www.semtech.com 1. pin out 1.1 gv7700 pin assignment figure 1-1: gv7700 pin out rsvd sdo_50_en din_19 din_17 din_15 din_14 din_12 din_10 din_8 din_7 din_5 din_4 din_3 din_2 din_0 fin hin vddio vddio_xout xtal_out vdd18_a xtal vdd18_a din_1 vddio vin n/c pclk n/c cap1 cap2 cap3 sdout sclk sdin div_1001 wclk aclk ain_3_4 xtal54_sel vddio vddio detect_trs vddio audio_en ain_1_2 hdvlc_en rsvd tdo trst tdi vddio cap4 vdd18_a vdd18_a vdd18_a vdd18_a vddio tck tms rsvd rsvd rsvd cap5 vdd18_a sdo vdd18_a rbias rsvd din_18 din_16 vddio din_13 din_11 din_9 din_6 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 b1 b2 b3 b4 b5 b6 b7 b8 b9 a36 a35 a34 a33 a32 a31 a30 a29 a28 a27 a26 a25 b27 b26 b25 b24 b23 b22 b21 b20 b19 b10 b11 b12 b13 b14 b15 b16 b17 b18 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 b34 b33 b32 b31 b30 b29 b28 b36 b35 a48 a47 a46 a45 a44 a43 a42 a41 a40 a39 a38 a37 sdo xtal_en bit20_bit10 reset cs xtal vddio threeg_hd
gv7700 final data sheet rev.7 pds-060377 december 2015 6 of 50 semtech www.semtech.com 1.2 pin descriptions table 1-1: gv7700 pin descriptions pin number name type description a1 rsvd connect to ground. a2 sdo_50_en input high = device outputs a 100 differential signal. low = device outputs a 75 single-ended output signal, with both complementary outputs on by default. each output can be manually disabled via gspi. schmitt trigger input with pull-down. b1 rsvd connect to ground. a3, b2, a4, b3, a5, a6, b5, a7, b6, a8 din_[19:10] input parallel data bus inputs [19:10]. if bit20_bit10 = high, the input data format must be word aligned, demultiplexed luma and chroma data. din_[19:10] are the input pins for luma data. if bit20_bit10 = low, the multiplexed luma and chroma data is presented on these pins. b7, a9, a10, b9, a11 a12, a13, a14, b10, a15 din_[9:0] input parallel data bus inputs [9:0]. if bit20_bit10 = high, the input data format must be word aligned, demultiplexed luma and chroma data. din_[9:0] are the input pins for chroma data. if bit20_bit10 = low, these pins are unused and should be tied to ground. b4, b8, b11, a18, b24, a36, a37, b32, b36 vddio power connect to 1.8v or 3.3v. a16 fin input field identification . used in interlaced mode. b12 vin input vertical blanking. a17 hin input horizontal blanking. b13 n/c do not connect. b14 pclk input 148.5mhz/74.25mhz input clock representing the time allocated to one 10 or 20-bit pixel. a19 vddio_xout power connect to 1.8v or 3.3v 1 . b15 n/c do not connect. a20 xtal_out analog output output capable of driving isp clock input. a21, a24, a26, b19, b20, b21, a29, b22 vdd18_a power connect to 1.8v. b16 cap1 analog input/output must connect to external decoupling filter. refer to figure 6-1: gv7700 typical application circuit .
gv7700 final data sheet rev.7 pds-060377 december 2015 7 of 50 semtech www.semtech.com b17 cap2 analog input/output must connect to external decoupling filter. refer to figure 6-1: gv7700 typical application circuit . a22 xtal analog input/output pin to external 27mhz or 54mhz crystal. when not using a crystal reference (xtal_en = high), connect xtal to ground. b18 cap3 analog input/output must connect to external decoupling filter. refer to figure 6-1: gv7700 typical application circuit . a23 xtal analog input/output pin to external 27mhz or 54mhz crystal. when not using a crystal reference (xtal_en = high), xtal can be left floating. a25 rbias analog input/output external 11k resistor for bias reference. connect the resistor to ground. a27, a28 sdo , sdo analog high-speed output serial differential output signal. single-ended operation at data rates of 2.97gb/s, 2.97/1.001gb/s, 1.485gb/s, 1.485/1.001gb/s, 540mb/s, or 270mb/s. b23 cap4 analog input/output must connect to external decoupling filter. refer to figure 6-1: gv7700 typical application circuit . a30 cap5 analog input/output must connect to external decoupling filter. refer to figure 6-1: gv7700 typical application circuit . a31 rsvd connect to ground. a32 rsvd this pin must be set high. b25 tdi input dedicated jtag pin C test data input. this pin is used to shift jtag test data into the device. schmitt trigger input with pull-up. if jtag is not used this pin may be left floating. a33 rsvd connect to ground. b26 trst input dedicated jtag pin C test reset. when set low, the jtag logic will be reset. schmitt trigger input with pull-up. if jtag is not used this pin must be pulled low. a34 tms input dedicated jtag pin C test mode select. this pin is used to control the operation of the jtag test. schmitt trigger input with pull-up. if jtag is not used this pin may be left floating. b27 tdo output dedicated jtag pin C test data output. this pin is used to shift results from the device. table 1-1: gv7700 pin desc riptions (continued) pin number name type description
gv7700 final data sheet rev.7 pds-060377 december 2015 8 of 50 semtech www.semtech.com a35 tck input dedicated jtag pin C serial data clock signal. this pin is the jtag clock. schmitt trigger input. if jtag is not used this pin must be pulled low. a38 xtal54_sel input high = for use with a 54mhz crystal. low = for use with a 27mhz crystal (default). schmitt trigger input with pull-down. b28 rsvd connect to ground a39 xtal_en input high = when using the pclk input as a frequency reference. low = when using an external xtal as a frequency reference. schmitt trigger input with pull-down. b29 hdvlc_en input high = enables hd-vlc compression for extended cable reach. low = disables hd-vlc compression. a40 ain_3_4 input i 2 s serial audio input; channels 3 and 4. schmitt trigger input. b30 ain_1_2 input i 2 s serial audio input; channels 1 and 2. schmitt trigger input. a41 aclk input serial audio input bit clock. serial bit clock for audio data from pins ain_1_2 and ain_3_4. schmitt trigger input. b31 audio_en input high = enables the device to support the insertion of 4 audio channels. low = disables device audio support. a42 wclk input serial audio left/right clock. word rate clock for the audio data from pins ain_1_2 and ain_3_4. supports sampling frequencies of 32khz, 44.1khz, and 48khz. schmitt trigger input. a43 div_1001 input high = enable device support for wh en the incoming frame rate is 60/1.001 or 30/1.001 frames per second. low = when the incoming frame rate is 60, 50, 30, or 25 frames per second. a44 threeg_hd input high = 3g video input. low = hd video input. b33 detect_trs input control signal input. used to select external hvf timing mode or trs extraction timing mode. low = the device extracts all internal timing from the supplied h:v:f. high = the device extracts all internal timing from trs signals embedded in the supplied video stream. table 1-1: gv7700 pin desc riptions (continued) pin number name type description
gv7700 final data sheet rev.7 pds-060377 december 2015 9 of 50 semtech www.semtech.com b34 reset input digital active-low reset input. used to reset the internal operating conditions to default settings. minimum reset duration of 10ms. see section 4.14 . device configuration pins should be set prior to device reset. schmitt trigger input. a45 bit20_bit10 input high = selects 20-bit wide input interface. low = selects 10-bit wide input interface. b35 cs input chip select input for the gennum seri al peripheral interface (gspi) host control/status port. active-low input. a46 sdin input serial data input for the gennum serial peripheral interface (gspi) host control/status port. a47 sclk input burst-mode clock input for the gennum serial peripheral interface (gspi) host control/status port. a48 sdout output serial data output for the gennum serial peripheral interface (gspi) host control/status port. center pad power common analog and digital ground conne ction, and main thermal path for device. notes: 1. serial output jitter increases by 10ps at 3.3v. table 1-1: gv7700 pin desc riptions (continued) pin number name type description
gv7700 final data sheet rev.7 pds-060377 december 2015 10 of 50 semtech www.semtech.com 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value supply voltage, digital i/o (vddio) -0.5v to +3.6v supply voltage, analog (vdd18_a) -0.5v to +2.5v dc input voltage, v in (except i/o pins) -0.5v to (vddio + 0.5v) dc output voltage, v out (except i/o pins) -0.5v to (vddio + 0.5v) input esd voltage (hbm) 2.5kv input esd voltage (cdm) 1kv storage temperature range (t s ) -50c to 125c operating temperature range (t a ) -40c to 85c solder reflow temperature (4s) 260c note: absolute maximum ratings are those values beyond which damage may occur. functional operation outside of the ranges shown in the ac and dc electrical characteristics is not guaranteed. table 2-2: dc electrical characteristics vdd18_a = 1.8v5% and ta = -20c to +85c unless otherwise stated parameter symbol conditions min typ max units notes supply voltage, digital i/o vddio 1.8v mode 1.71 1.8 1.89 v 3.3v mode 3.13 3.3 3.47 v supply voltage, analog vdd18_a 1.71 1.8 1.89 v supply current, digital i/o i ddio 1.8v mode 0.25 0.5 ma 3.3v mode 3.5 4.75 ma supply current, analog i dd18_a 100 115 ma 1
gv7700 final data sheet rev.7 pds-060377 december 2015 11 of 50 semtech www.semtech.com 2.3 ac electrical characteristics total power consumption p total hd mode 140 170 mw 2 3g mode 160 180 mw 2 270 mode 180 215 mw 2 540 mode 240 275 mw 2 external rbias resistor 10.89 11 11.1 k power supply noise mask 0hzC1.5ghz 20 mv pp 3 digital logic input v il input low -0.3 0.63 v v ih input high 1.17 3.465 v digital logic output v ol output low 0.45 v v oh output high 1.35 v notes: 1. sd mode. 2. max = 85c, vdd18_a = 1.89v. 3. using recommended power supply decoupling. see figure 6-1: gv7700 typical application circuit . table 2-2: dc electrical characteristics (continued) vdd18_a = 1.8v5% and ta = -20c to +85c unless otherwise stated parameter symbol conditions min typ max units notes table 2-3: ac electrical characteristics vdd18_a = 1.8v5% and ta = -20c to +85c unless otherwise stated parameter symbol conditions min typ max units notes input conditions input pclk clock frequency 10-bit mode 148.5 mhz 1 20-bit mode 74.25 mhz 1 , 3 pclk duty cycle dc pclk 40 60 % input data setup time t su 1.2 ns input data hold time t hold 0.8 ns output driver impedance 75 single-ended 66 75 84 100 differential 88 100 112
gv7700 final data sheet rev.7 pds-060377 december 2015 12 of 50 semtech www.semtech.com return loss 1mhz - 5mhz 17.9 db 5mhz - 1.485ghz 6.7 db 1.485ghz - 2.25ghz 4 db amplitude 75 single-ended 0.36 0.8 0.9 v pp 100 differential 0.36 0.8 0.9 v ppd rise/fall time 100 differential 20% - 80% 8595ps 75 single-ended 20% - 80% 102 150 ps rise/fall time mismatch 20% - 80% 50 ps overshoot 10 % output total jitter data rate = 270mb/s 0.021 ui pp 2 data rate = 540mb/s 0.04 ui pp 2 data rate = 1.485gb/s 0.115 ui pp 2 data rate = 2.97gb/s 0.2 ui pp 2 de-emphasis post-cursor 0 1 db crystal oscillator external crystal reference frequency 27 or 54 mhz load capacitance 8 9 pf start-up time 100 ms accuracy 20 100 ppm gspi digital control gspi read/write clock frequency 40mhz reset time 10 ms register access time 300 ns notes : 1. if div_1001 = high, divide the listed pclk frequency by 1.001. 2. jitter performance is only guaranteed when using a crystal (27/ 54mhz) as the clock reference for the device. jitter performan ce is not guaranteed when using the pclk clock generated by the isp as the reference for the device. 3. in 3g 20-bit mode, the pclk is 148.5mhz. table 2-3: ac electrical ch aracteristics (continued) vdd18_a = 1.8v5% and ta = -20c to +85c unless otherwise stated parameter symbol conditions min typ max units notes
gv7700 final data sheet rev.7 pds-060377 december 2015 13 of 50 semtech www.semtech.com 3. input/output circuits figure 3-1: serial output driver figure 3-2: rbias 50/75 output drive impedance level & de-emphasis control level & de-emphasis control ch[0:3]_sdo_n ch[0:3]_sdo_p gnd esd clamp 1.8v vdda18_drv rbias to clamp
gv7700 final data sheet rev.7 pds-060377 december 2015 14 of 50 semtech www.semtech.com 4. detailed description 4.1 functional overview the gv7700 is a low cost, dual-rate hdcc tv transmitter with integrated hd-vlc encoding. with integrated cable driving technology, the gv7700 is capable of transmitting compressed video at 270mb/s or 540mb/s, or uncompressed video at 1.485gb/s or 2.97gb/s, over 75 coaxial cable. compressed si gnals can also be transmitted differentially ov er 100 twisted pair cable. the high definition visually lossless codec (hd-vlc?) technology is integrated in order to reduce the transmission data rate of hd video over both coaxial and unshielded twisted pair (utp) cable. this is achieved by encoding the hd-sdi video, normally transmitted at a serial data rate of 1.485gb/ s, to the same rate as standard definition (sd-sdi) video, at 270mb/s serial data rate. this provides extended cable reach for hd video up to 550m over belden 543945 cctv co ax or 150m over cat-5e/6 utp cable. similarly, 3g-sdi normally transmitted at 2.97gb/s can be encoded down to 540mb/s. the gv7700 features an audio embedding core, which supports up to 4 channels of i 2 s serial digital audio within the ancillary data space of the video data stream. the audio embedding core supports 32khz, 44.1khz, and 48khz sample rates. the device allows for both 8-bit and 10-bit per pixel ycbcr 4:2:2 bt.1120 component digital video. a configurable 20-bit wide para llel digital video input bus is provided, with associated pixel clock and h/v/f timing signal inputs. the gv7700 supports the insertion of ancillar y data into the horizontal blanking of the video data stream. user data can be prog rammed via the gspi, allowing downstream communication from the video so urce to sink device. the an cillary data packing format is compliant with hdcctv 2. 0 communications protocol. the device includes a 4-wire gennum serial peripheral interface (gspi 2.0) for external host command and control. all read or write access to the gv7700 is initiated and terminated by the application host processor. the host interface is provided to allow optional configuration of some of the functions and operating modes of the gv7700. it is recommended to use the integrated low-noise crystal oscillator and an external crystal as the primary reference clock for th e gv7700. this configuration will yield the optimal jitter performance. degraded performance will likely occur when using a pclk input from the isp which typically has much more jitter. a derived clock must be used as the clock reference by the image signal processing (isp) ic to avoid any frequency mismatch. in this case, connect the gv7700s xtal_out pin to the isps reference frequency input. crystal values of 27mhz or 54mhz may be used, depending on the isp requirement. xtal54_sel must be high when using a 54mhz crystal and low when using a 27mhz crystal. jitter performance is only guaranteed when using a crystal (27/54mhz) as the clock reference for the device. jitter performance is not guaranteed when using the pclk clock generated by the isp as the reference for the device.
gv7700 final data sheet rev.7 pds-060377 december 2015 15 of 50 semtech www.semtech.com 4.2 parallel video data inputs din_[19:0] data signal inputs enter the device on the rising edge of pclk, as shown in figure 4-1 . figure 4-1: gv7700 video interface timing diagram the gv7700 is a high performance serial digital video and audio transmitter. source series termination resistors should be used to minimize reflections on the parallel video data inputs, pclk, audio inputs, and h, v, f ti ming input signals. this will ensure that signals are received correctly by the gv7700. resi stors must be plac ed at the signal source away from the gv7700 inputs. 4.2.1 parallel input in video mode data must be presented to the input bus in either multiplexed or demultiplexed form, depending on the setting of the bit20_bit10 pin. when operating in 20-bit mode (bit20_bit10 = high), the input data format must be word aligned, demultiplexe d luma and chroma data. th e luma (y) data must be presented on the din[19:10] pins, and the ch roma (cb/cr) data must be presented on the din[9:0] pins. when operating in 10-bit mode (bit20_bit10 = low), the input data format must be word aligned, multiplexed luma and chroma data. in this mode, the data must be presented on the din[19:10] pins. the din[9:0] inputs are ignored and should be tied to ground. ddr interface note: ds = data stream as per st 425 data_* is launched on the posedge of pclk by the source chip, to the gv7700 sdr interface ds2_0 ds1_0 ds1_n-1 ds1_n-1 transition zone ds2_0 transition zone ds1_0 transition zone ds2_* is launched on the negedge of pclk by the source chip to the gv7700 ds1_* is launched on the posedge of pclk by the source chip to the gv7700 3.36ns pclk din[19:10], fin, hin, vin t su t h t su t h data_0 transition zone data_0 data_1 transition zone data_1 pclk period t su t h t su t h pclk din[19:0], fin, hin, vin table 4-1: gv7700 parallel input ac electrical characteristics parameter symbol conditions min typ max units input data set-up time t su 50% levels; 1.8v operation 1.2 ns input data hold time t h 0.8 ns
gv7700 final data sheet rev.7 pds-060377 december 2015 16 of 50 semtech www.semtech.com when operating in 10-bit mode (bit20_b it10 = low) with 3g video (threeg_hd = high), the pclk input is ddr 148.5mhz. 4.2.1.1 high defi nition video input formats itu-r bt.1120 describes the serial and parallel format for 1080-line interlaced and progressive digital video. the field/frame bl anking period (v), the line blanking period (h), and the field identification (f), are e mbedded as digital timing codes (trs) within the video. data is transmitted over two 10-bit buses, one for luma (y') and one for colour difference (c' b c' r ), operating at a clock rate of 74.25mhz or 74.25/1.001mhz. the following figures show horizontal and vertical timing for 1080-line interlaced systems. figure 4-2: field timing relationship for 1080-line interlaced systems figure 4-3: luma stream over one video line - 1080i blanking blanking 1 blanking blanking 20 21 560 561 563 564 583 584 1123 1124 1125 field 1 active video v=0 v=1 field 1 (f=0) odd h=1 eav field 2 (f=1) even h=0 sav field 2 active video v=1 v=0 v=1 line start of digital line eav code sav code blanking h control signal start of digital active line next line 1920 y stream h1 h2 3ff 000 xyz ln0 ycr0 ln1 ycr1 ya1 ya0 000 000 000 3ff 3ff ya2 ya(n-1) xyz yd0 yd1 yd2 yd3 yd4 yd5 yd6 yd7 yd1918 yd1919
gv7700 final data sheet rev.7 pds-060377 december 2015 17 of 50 semtech www.semtech.com figure 4-4: chroma stream over one video line - 1080i figure 4-5: multiplexed luma and ch roma over one video line - 1080i 4.2.1.2 high defi nition 1080p input formats itu-r bt.1120 also includes pr ogressive scan formats with 10 80 active lines, with y'c' b c' r 4:2:2 sampling at pixel rates of 74.25mhz or 74.25/1.001mhz. the following diagrams show horizontal and vertical timing for 1080-line progressive systems. figure 4-6: frame timing relationshi p for 1080-line progressive systems start of digital line eav code sav code blanking h control signal start of digital active line next line 1920 h1 h2 3ff 000 xyz ln0 ccr0 ln1 000 000 000 3ff 3ff xyz crd959 c /c stream b r ccr1 ca0 ca1 ca2 ca(n-1) cbd0 crd0 cbd1 crd1 cbd2 crd2 cbd3 crd3 cbd959 start of digital line eav code sav code blanking start of digital active line next line multiplexed stream 3ff 000 xyz ln0 ccr0 ln1 000 000 000 3ff 3ff xyz ycr0 3ff 000 000 3ff 000 000 xyz ln0 ln1 3ff xyz ccr1 ycr1 ca0 ya0 ca1 ya1 ca2 ya2 ca(n-1) ya(n-1) cbd0 yd0 crd0 yd1 cbd1 yd2 cbd959 yd1918 crd959 yd1919 table 4-2: 1080-line interlaced horizontal timing interlaced 60hz or 60/1.001hz 50hz h1 280 720 h2 2200 2640 active video blanking blanking 1 41 42 1121 1122 1125 v=0 v=1 (f=0) h=1 eav h=0 sav v=1 line
gv7700 final data sheet rev.7 pds-060377 december 2015 18 of 50 semtech www.semtech.com figure 4-7: luma stream over one video line - 1080p figure 4-8: chroma stream over one video line - 1080p figure 4-9: multiplexed luma and ch roma over one video line - 1080p start of digital line eav code sav code blanking h control signal start of digital active line next line 1920 y stream h1 h2 3ff 000 xyz ln0 ycr0 ln1 ycr1 ya1 ya0 000 000 000 3ff 3ff ya2 ya(n-1) xyz yd0 yd1 yd2 yd3 yd4 yd5 yd6 yd7 yd1918 yd1919 start of digital line eav code sav code blanking h control signal start of digital active line next line 1920 h1 h2 3ff 000 xyz ln0 ccr0 ln1 000 000 000 3ff 3ff xyz crd959 c /c stream b r ccr1 ca0 ca1 ca2 ca(n-1) cbd0 crd0 cbd1 crd1 cbd2 crd2 cbd3 crd3 cbd959 start of digital line eav code sav code blanking start of digital active line next line multiplexed stream 3ff 000 xyz ln0 ccr0 ln1 000 000 000 3ff 3ff xyz ycr0 3ff 000 000 3ff 000 000 xyz ln0 ln1 3ff xyz ccr1 ycr1 ca0 ya0 ca1 ya1 ca2 ya2 ca(n-1) ya(n-1) cbd0 yd0 crd0 yd1 cbd1 yd2 cbd959 yd1918 crd959 yd1919 table 4-3: 1080-line progressive horizontal timing progressive 30hz, 30/1.001hz, 60hz, 60/1.001hz 25hz or 50hz 24hz or 24/1.001hz h1 280 720 830 h2 2200 2640 2750
gv7700 final data sheet rev.7 pds-060377 december 2015 19 of 50 semtech www.semtech.com 4.2.1.3 high defi nition 720p input formats the society of motion picture and television engineers (smpte) defines the standard for progressive scan 720-line hd image form ats. smpte st 296-2001 specifies the representation for 720p digital y'c' b c' r 4:2:2 signals at pixel rates of 74.25mhz or 74.25/1.001mhz. figure 4-10: 720p digital vertical timing the frame rate determines the horiz ontal timing, which is shown in table 4-4 . active video blanking blanking 1 25 26 745 746 750 v=0 v=1 (f=0) h=1 eav h=0 sav v=1 line table 4-4: 720p horizontal timing frame rate h = 1 sample number h = 0 sample number total samples per line 25 1280 0 3960 30 or 30/1.001 1280 0 3300 50 1280 0 1980 60 or 60/1.001 1280 0 1650
gv7700 final data sheet rev.7 pds-060377 december 2015 20 of 50 semtech www.semtech.com 4.2.1.4 3g-sdi 1080p input formats the society of motion picture and television engineers (smpte) defines the standard for 3g-sdi image formats in st 425. the gv7700 supports 1080p50/60 y'c' b c' r 4:2:2 8/10-bit. figure 4-11: 20-bit mapping structure for 1920 x 1080 50/60hz progressive 4:2:2 (ycbcr) 8/10-bit signals optional ancillary data space optional ancillary data space y data (interface clock frequency= 148.5 mhz or 148.5/1.001 mhz) replaced by timing reference signal replaced by line number replaced by line crc replaced by timing reference signal c data (interface clock frequency= 74.25 mhz or 74.25/1.001 mhz) b c data (interface clock frequency= 74.25 mhz or 74.25/1.001 mhz) r data stream 1 (interface clock frequency= 148.5 mhz or 148.5/1.001 mhz) data stream 2 (interface clock frequency= 148.5 mhz or 148.5/1.001 mhz) for 60 or 60/1.001, n=2199 for 50, n=2639 y 1918 y 1919 y 1920 y 1921 y 1922 y 1923 y 1924 y 1925 y 1927 y (n-3) y (n-2) y 1926 y n last sample y 0 y 1 y 2 y 3 c 959 b c 960 b c 961 b c 962 b c 963 b c 960 r c (n-1) b c 961 r c 959 r c 962 r c 963 r y (n-1) c n last sample b c (n-1) r c 0 b c 1 b c 0 r c 1 r c n last sample r y 1918 y 1919 y 0 y 1 y 2 y 3 c 959 b c 959 r c 0 b c 1 b c 0 r c 1 r eav (3ffh) eav (000h) eav (000h) eav (xyz) ln0 ln1 crc0 crc1 sav (3ffh) sav (000h) sav (000h) sav (xyz) eav (3ffh) eav (000h) eav (000h) eav (xyz) ln0 ln1 crc0 crc1 sav (3ffh) sav (000h) sav (000h) sav (xyz)
gv7700 final data sheet rev.7 pds-060377 december 2015 21 of 50 semtech www.semtech.com note: for 8-bit systems, the data should be just ified to the most significant bit (y9 and c b c r 9), with the two le ast significant bits (y[1:0] and c b c r [1:0]) set to zero. 4.3 video processing the gv7700 is designed to carry out data scrambling according to itu-r bt.1120, and to carry out nrz to nrzi encoding prior to presentation to the parallel to serial converter. 4.3.1 h:v:f timing the gv7700 can automatically detect the vid eo standard and gene rate all internal timing signals. the total line length, act ive line length, total number of lines per field/frame and total active lines per field/frame are calculated for the received parallel video. when detect_trs is low, the video standa rd and timing signals are based on the externally supplied horizontal blanking, vertical blanking, and field identification signals. these signals go to th e hin, vin, and fin pins respectively. when detect_trs is high, the video standard timing signals ar e extracted from the embedded trs id words in the parallel input data. both 8-bit and 10 -bit trs code words are identified by the device. the gv7700 determines the video standard by timing the horizontal and vertical reference information supplied at the hin, vi n, and fin input pins, or contained in the trs id words of the received video data. therefore, full synchronization to the received video standard requires at le ast one complete video frame. once synchronization has been achieved, the gv7700 continues to monitor the received trs timing or the supplied h, v, and f timing information to maintain synchronization. the gv7700 loses all timing information immediately following loss of h, v, and f. the timing of these signals is shown in figure 4-12 to figure 4-13 below. table 4-5: 1080p yc b c r 4:2:0 & 4:2:2 10-bit bit structure mapping data stream bit number 9 8 7 6 5 4 3 2 1 0 ds1 y[9:0] ds2 c b c r [9:0]
gv7700 final data sheet rev.7 pds-060377 december 2015 22 of 50 semtech www.semtech.com figure 4-12: h:v:f input timi ng hd 20-bit input mode figure 4-13: h:v:f input timi ng hd 10-bit input mode 4.4 hd-vlc? encoder the gv7700 integrates the high definition visually lossless co dec (hd-vlc) encoder for extended reach video transmission. when used in conjunction with the gv7704 hd-vlc quad receiver, hd vid eo transmission can be ex tended significantly over existing hd serial digital video systems. hd-vlc is based on a simple visually lossless implementation of the dirac compression tool kit. the visually lossless encoder is used to reduce the video bandwidth, using a very low latency mode , from a transmission rate of 1.485gb/s (hd-sdi) to 270mb/s (sd-sdi). at a data rate of 270mb/s, the serial digi tal encoded hd video ca n be transmitted over longer runs of coaxial cable. table 4-6 below shows a comparison of cable distances between hd video transmission at 1.485g b/s and hd-vlc encoded at 270mb/s for various common coaxial cable types. pclk din_ [19:10] yn -1 3ff h 000 h 000 h eav ln 0 ln 1 din_[9:0] cn -1 3ff h 000 h 000 h eav ln 0 ln 1 hin vin fin yn -2 cn -2 yn -3 cn -3 3ff h 000 h 000 h sav 3ff h 000 h 000 h sav crc 0 crc 1 crc 0 crc 1 blk blk y0 cb 0 y1 y2 cr 0 cb 2 yn -1 3ff h 000 h 000 h eav ln 0 ln 1 cn -1 3ff h 000 h 000 h eav ln 0 ln 1 yn -2 3ff h 000 h 000 h sav 3ff h 000 h 000 h crc 0 crc 1 crc 0 crc 1 y0 cb 0 cr 0 sav not used pclk din_ [19:10] din_[9:0] hin vin fin not used not used table 4-6: cable reach for variou s cable types (in meters) cable type hd-vlc: 270mb/s (m) hd-vlc: 540mb/s (m) hd-sdi: 1.485gb/s (m) 3g-sdi: 2.97gb/s (m) belden 1694a / canare l-4.5chd 710 500 230 160 belden 543945 550 400 150 100 kw-link syv 75-5 500 350 140 100 canare l-3c2v 300 200 95 70 kw-link syv 75-3 300 200 80 60 note: these values apply for new, properly terminated cables. actual performance may vary.
gv7700 final data sheet rev.7 pds-060377 december 2015 23 of 50 semtech www.semtech.com after transmission over the coaxial cable, the 270mb/s serial data is recovered using the gv7704 hd-vlc quad receiver and the data decoded back to the native hd format. the encoding and decoding proce ss has a total latency of 12-1 4 hd lines, which makes the codec ideal for low latenc y real-time applications. table 4-7 below shows the total encode/decode latency through the gv7700 and the gv7704. the hd-vlc encoder can be enabled by se tting the hdvlc_en input pin high. when this pin is set high, the gv7700 will ou tput hd encoded video at 270mb/s and 3g encoded video at 540mb/s. conf iguration pins should be se t prior to device reset. the 270mb/s data stream uses the same timing and frame structure as standard definition sdi (sd-sdi), and can be monitored using st andard sd-sdi test equipment to check signal integrity. however, th e data contained within the active picture area of the sd-sdi stream contains only encoded hd packets. the hd video content can only be viewed after the hd-vlc decoding process. when the gv7700 is hd-vlc encoding video formats at true 30 or 60 frames per second, the 270mb/s (540mb/s) serial data output will actually operate at 270x1.001mb/s (540x1.001mb/s). this multiplication factor is to account for the fractional increase in the orig inal hd video frame rate. for all other hd frame rates, the gv7700 serial data output will be exactly 270mb/s (540mb/s). 4.5 stream id packet insertion the gv7700 will always insert stream id packets immediately after the crc1 word of the y channel if the chip is in reclocker mode (hdvlc_en = 0) or immediately after the crc1 word of the ycbcr multiplexe d data if the chip is in hd-vlc compression mode (hdvlc_en = 1). table 4-7: encode and decode total latency (gv7700 + gv7704) video format delay (s) delay (hd/3g lines) 1080p25 422.2 11.9 1080p29.97 368.8 12.4 1080p30 368.4 12.4 720p25 635.1 11.9 720p29.97 546.6 12.2 720p30 546.6 12.2 720p50 368.6 13.8 720p59.94 324.2 14.5 720p60 324.2 14.5 1080p60 184.2 12.4 1080p59.94 184.4 12.4 1080p50 211.1 11.9
gv7700 final data sheet rev.7 pds-060377 december 2015 24 of 50 semtech www.semtech.com the chip will insert the stream id packet on the following lines shown in table 4-8 below. table 4-8: stream id line insertion for video standards input video standard hdvlc_en output video standard line number for insertion 720p25 0 720p25 8 1 625i50 7, 320 720p29.97 0 720p29.97 8 1 525i59.94 11, 274 720p30 0 720p30 8 1 525i60 11, 274 720p50 0 720p50 8 1 625i25 7, 320 720p59.94 0 720p59.94 8 1 525i29.97 11, 274 720p60 0 720p60 8 1 525i30 11, 274 1080p25 0 1080p25 8 1 625i25 7, 320 1080p29.97 0 1080p29.97 8 1 525i29.97 11, 274 1080p30 0 1080p30 8 1 525i30 11, 274 1080i50 0 1080i50 8, 570 1 625i25 7, 320 1080i59.94 0 1080i59.94 8, 570 1 525i29.97 11, 274 1080p60 0 1080p60 8 1 525i69 11, 274 1080p59.94 0 1080p59.94 8 1 525i59.94 11, 274 1080p50 0 1080p50 8 1 625i50 7, 320
gv7700 final data sheet rev.7 pds-060377 december 2015 25 of 50 semtech www.semtech.com 4.6 audio embedding the gv7700 includes an audio multiplexer, which is enabled by setting the audio_en pin high. the device will embed audio in both hd and hd-vlc encoding modes. the gv7700 can embed up to four channels of serial digital audio at an audio sampling rate of 32khz, 44.1khz, or 48khz. 4.6.1 serial audio data inputs the gv7700 supports the insertion of up to 4 channels of embedded audio, in one audio group according to smpte st 299. when in hd-vlc mode (hdvlc_en = 1), the audio data packets will be inserted in the ycbcr multiplexed data . when hd-vlc encoding is disabled (hdvlc_en = 0), the audio data packets will be inserted in the c channel of the hd signal as per smpte st 299. the four audio channels must be input as 2- channel pairs, timed to a serial bit clock (aclk) at a frequency of 64*? s , and a word clock (wclk) at a frequency of ? s , where ? s can be 32khz, 44.1khz, or 48khz. the serial audio input format must conform to i 2 s. the serial audio input signals and wclk input signals enter the device on the rising edge of aclk as shown in figure 4-14 . the audio sampling frequency can be programm ed from the host interface by writing to the audio_sampling_freq bi ts in register 109. see table 4-9 below. figure 4-14: aclk to audio data and wclk signal input timing table 4-9: audio sampling frequency selection audio_sampling_freq input audio sampling rate 00 48khz 01 44.1khz 10 32khz aclk data data ain_1_2, ain_3_4 wclk t ih t su
gv7700 final data sheet rev.7 pds-060377 december 2015 26 of 50 semtech www.semtech.com 4.6.2 serial i 2 s audio data format the gv7700 supports the i 2 s serial audio data format, as shown in figure 4-15 below. figure 4-15: i 2 s audio input format 4.6.3 audio mute the gv7700 can mute either pair of input audio channels using 2 host interface control bits. the bits can mute channels 1 & 2 or channels 3 & 4. channels 1 & 2 can be muted by asserting the mute_1_2 bit in the aud_ins_ ctrl_reg register. channels 3 & 4 can be muted by asserting the mute_3_4 bit in the aud_ins_ctrl_reg register. see table 4-11 . by default, the 4 channels will not be muted. 4.6.4 ecc error detection and correction for audio embedding in hd video formats, th e packeted audio sample data is protected from bit errors using error correction codes (ecc). the error correction codes are carried in the same packet as the audio sample data for error detection and correction in the gv7704 receiver. the gv7700 uses bch(31,25) code for ecc. the gv7700 automatically gene rates the error detection and correction fields in the audio data packets. table 4-10: gv7700 serial audio data inpu ts - ac electrical characteristics parameter symbol conditions min typ max units input data set-up time t su 50% levels; 1.8v operation 1.3 ns input data hold time t ih 45 ns wclk aclk ain[4/3:2/1] msb 6 22 lsb channel a (left) channel b (right) 23 54321 0 6 22 lsb 54321 0 23 msb table 4-11: audio mute controls address parameter description 486f h [1:1] mute_3_4 high = channels 3 & 4 are muted low = channels 3 & 4 are not muted 486f h [0:0] mute_1_2 high = channels 1 & 2 are muted low = channels 1 & 2 are not muted
gv7700 final data sheet rev.7 pds-060377 december 2015 27 of 50 semtech www.semtech.com 4.7 ancillary data insertion the horizontal blanking region of a digital video signal may be used to carry ancillary data packets. the vertical bl anking region is used by the hd-vlc encoder which inserts compression coefficients which cannot be overwritten. the payload of the ancillary data packet can be used to carry user-defined or proprietary data, which can be sent between an aviia transmitter and receiver. the ancillary data packet is formatted according to the figure 4-16 below. the packet must always begin with the ancillary data flag (adf), defined as the following 10-bit word sequence: 000 h , 3ff h , 3ff h . the next data word is the 8-bit data id (did), used to define the contents of the packet. for example, a unique did ca n be used to denote alarm data, with another did to denote status data. the 8-bit did is wr itten to the anc_ins_did bits of the anc_ins_did_reg register. after the did insertion, there are two possible options, as shown in figure 4-16 . figure 4-16: ancillary data packets a type 1 packet defines an 8-bit data block number (dbn) sequence, used to distinguish successive packets with the same did. the dbn simply increments with each packet of the same did, between 0 and 15. for a type 2 packet, an 8-bit secondary data id (sdid) word is defined, which can be used to denote variants of payloads with the same did. for example, packets with a did to denote error data may dist inguish different error types us ing unique sdid's. the sdid or dbn word is written to the anc_ins_sdid bits of the anc_ins_sdid_reg register. after the dbn or sdid, the next data word is the 8-bit data count (dc). this word must be set to the number of user data words (u dw) that follow the dc, and must not exceed 16 (maximum payload size). the data count (dc) word is written to the anc_ins_dc bits of the anc_ins_dc_reg register. the valid range for this word is 00000001 b to 00010000 b . user data words msb lsb parity bit type 1 anc illary data packet user data words not b8 parity bit type 2 anc illary data packet msb lsb not b8 adf did dbn dc udw0 udw1 udw2 udw3 cs adf did sdid dc cs udw14 udw13 udw12 udw11 udw10 udw9 udw8 udw7 udw6 udw5 udw4 udw15 udw0 udw1 udw2 udw3 udw14 udw13 udw12 udw11 udw10 udw9 udw8 udw7 udw6 udw5 udw4 udw15
gv7700 final data sheet rev.7 pds-060377 december 2015 28 of 50 semtech www.semtech.com the final word of the ancillary data packet is the 9-bit checksum (cs). the cs value must be equal to the nine least sign ificant bits of the sum of the nine least significant bits of the did, the dbn or the sdid, the dc and all user data words (udw) in the packet. the cs value is automatically calculated by the gv 7700, so no user configuration is required. for hd video formats, the gv7700 only in serts ancillary data packets in the luma channel. data words may be inserted on any line in the horizontal blanking region by writing the line number to the two bit slic es anc_ins_line_number_10_8 and anc_ins_line_number_7_0. the three most significant bits of the line number (bits 10:8) are written to anc_ins_line_number_10_8, and the remainin g eight bits (bits 7:0) are written to anc_ins_line_number_7_0. an example is illustrated in table 4-12 below. up to 23 data words may be inserted per frame with all data words including the ancillary packet adf, did, sdid/dbn, dc, and csum words being provided by the user via host interface configuration. user configuration of the ancillary data insertion function incl udes the following information: ? line number for insertion any line in the horizontal blanking region may be programmed for ancillary data insertion ? total number of words to insert includes all data words for all ancillary packets to be inserted on each line ? ancillary data up to 23 user data words may be inserted ? operating mode two modes of operation can be selected: ? continuous mode (anc_ins_select = 0) the data packet will be inserted continuously each time the current line number equals the line number specified through the anc_ins_line_number_10_8 and anc_ins_line_number_7:0 bits in the host interface. ? one-time mode (anc_ins_select = 1) th e data packet will be inserted once, and then it will not be inserted again un til the host resets the anc_ins_enable signal low, and then sets it high. table 4-12: examples of ancillary data insertion line number selection anc_ins_line_ number_10_8 anc_ins_line_number_7_0 horizontal line number insertion 000 00000001 1 100 01100101 1125
gv7700 final data sheet rev.7 pds-060377 december 2015 29 of 50 semtech www.semtech.com 4.8 additional processing functions 4.8.1 test pattern generation the gv7700 supports test pattern generation through csr configuration. two types of patterns are supported: ? flat-field pattern (a single programmable colour for the whole active picture) ? pathological pattern test pattern generation is enabled via the insert_test_pat_ enable bit of the tpg_ctrl_reg register. when this bit is high, test patterns are inserted into the active picture region of the incoming video data. the type of test pattern is determined by the pattern_sel bit of the tpg_ctrl_reg register, shown in table 4-13 below. the following is an example of how to program a flat-field red test pattern (pattern_sel = 1). the pixel setting registers, and the required values to write to the registers, are shown in table 4-14 below. note that when hd-vlc encoding is enabled, the pixel registers are programmed with the same values as when hd-vlc encoding is disabled. table 4-13: test pattern type selection pattern_sel output test pattern 0pathological 1flat-field
gv7700 final data sheet rev.7 pds-060377 december 2015 30 of 50 semtech www.semtech.com in order to generate a pathological test pa ttern as per smpte recommended practice rp 198, the gv7700 should be configured as shown in table 4-15 below. table 4-14: flat-field red test pattern parameter bit value pixel value channel outputs (hdvlc_en = 0) channel outputs (hdvlc_en = 1) pixel0_y0_9_8 0 d 0fc h y channel: 0fc h C 0fc h C 0fc h C 0fc h C 0fc h C 0fc h C 0fc h C 0fc h ... ycbcr channel: 198 h C 0fc h C 3c0 h C 0fc h C 198 h C 0fc h C 3c0 h C 0fc h ... pixel0_y0_7_0 252 d pixel0_y1_9_8 0 d 0fc h pixel0_y1_7_0 252 d pixel0_cb0_9_8 1 d 198 h c channel: 198 h C 3c0 h C 198 h C 3c0 h C 198 h C 3c0 h C 198 h C 3c0 h ... pixel0_cb0_7_0 152 d pixel0_cr0_9_8 3 d 3c0 h pixel0_cr0_7_0 192 d note: all pixel1 registers, from register address 48a0 h to 48a7 h , are not required for programming flat-field test patterns. they may all be set to 0000 h
gv7700 final data sheet rev.7 pds-060377 december 2015 31 of 50 semtech www.semtech.com the line that the pathological test signal will transition on is dependent on the output video format. the transition point should be consistent from frame to frame, and from field to field if the vid eo is interlaced. see table 4-16 below on how to program the transitional line number. table 4-15: pathological test pattern (smpte rp 198 recommended) parameter bit value pixel value channel outputs equalizer test signal pixel0_y0_9_8 1 d 198 h y channel: 198 h C 198 h C 198 h C 198 h C 198 h C 198 h C 198 h C 198 h ... pixel0_y0_7_0 152 d pixel0_y1_9_8 1 d 198 h pixel0_y1_7_0 152 d pixel0_cb0_9_8 3 d 300 h c channel: 300 h C 300 h C 300 h C 300 h C 300 h C 300 h C 300 h C 300 h ... pixel0_cb0_7_0 0 d pixel0_cr0_9_8 3 d 300 h pixel0_cr0_7_0 0 d pll test signal (see note 1 ) pixel1_y0_9_8 1 d 110 h y channel: 110 h C 110 h C 110 h C 110 h C 110 h C 110 h C 110 h C 110 h ... pixel1_y0_7_0 16 d pixel1_y1_9_8 1 d 110 h pixel1_y1_7_0 16 d pixel1_cb0_9_8 2 d 200 h c channel: 200 h C 200 h C 200 h C 200 h C 200 h C 200 h C 200 h C 200 h ... pixel1_cb0_7_0 0 d pixel1_cr0_9_8 2 d 200 h pixel1_cr0_7_0 0 d note: 1. transition from the equalizer test signal to the pll test signal occurs according to table 4-16 below. table 4-16: pathological test signal transition line video format patho_pll_line_f1 patho_pll_line_f2 1080i50 384 d 973 d 1080i59.94 288 d 851 d 1080p25 697 d n/a
gv7700 final data sheet rev.7 pds-060377 december 2015 32 of 50 semtech www.semtech.com 4.8.2 trs generation and insertion the gv7700 is capable of generating and inserting trs codes. trs word generation and insertion are performed in accordance with the timing parameters generated by the timing circui ts, which are locked to the externally provided h:v:f signals, or the trs sign als embedded in the input data stream. 10-bit trs code words ar e inserted at all times. 4.8.3 hd line number calculation and insertion the gv7700 is capable of line number generation and insertion, in accordance with the relevant hd video standard, as determined by the automa tic video standard detector. the gv7700 generates and inse rts line numbers into both the y and c channels of the data stream when hdvlc_en = 0, and genera tes and inserts line numbers in the ycbcr multiplexed stream when hdvlc_en = 1. 4.8.4 line based crc generation and insertion the gv7700 generates and inse rts line based crc words into both the y and c channels of the data stream when hdvlc_en = 0, an d generates and inserts line based crc words in the ycbcr multiplexed stream when hdvlc_en = 1. 4.8.5 illegal code re-mapping the gv7700 detects and corrects illegal code words within the active picture area. all codes within the active picture (outside the horizontal and vert ical blanking periods), between the values of 3fc h and 3ff h are re-mapped to 3fb h . all codes within the active picture area between the values of 000 h and 003 h are remapped to 004 h . 8-bit trs code words and ancillary data prea mbles are also re-mapped to 10-bit values. 4.9 parallel to serial conversion the parallel data output of the internal data processing blocks is fed to the parallel to serial converter. note : the internal data path bus width is inde pendent of the parallel data bus input bus width, which is controlled by the setting of the bit20_bit10 pin. 1080p30/29.97 579 d n/a 720p (all frame rates) 383 d n/a table 4-16: pathological test sign al transition line (continued) video format patho_pll_line_f1 patho_pll_line_f2
gv7700 final data sheet rev.7 pds-060377 december 2015 33 of 50 semtech www.semtech.com 4.10 pll internal division ratios for th e pclk are determined by the setting of the hdvlc_en pin, the bit20_bit10 pin and the div_1001 pin as shown in table 4-17 : as well as generating the serial digital outp ut clock signals, the pl l is also responsible for generating all internal cloc k signals required by the device. 4.10.1 frequency reference the frequency reference for the gv7700 pll can either be the pclk input or an external crystal. while using an external xtal as the frequency reference, set the input pin xtal_en low. two pins, xtal and xtal , are provided to connect to the external crystal. table 4-17: pclk and seri al digital clock rates external pin setting supplied pclk rate serial digital output rate notes threeg_hd hdvlc_en bit20_bit10 div_1001 low high high low 74.25mhz 270mb/s 1 low high high high 74.25/1.001mhz 270mb/s low high low low 148.5mhz 270mb/s 1 low high low high 148.5/1.001mhz 270mb/s low low high low 74.25mhz 1.485gb/s low low high high 74.25/1.001mhz 1.485/1.001gb/s low low low low 148.5mhz 1.485gb/s low low low high 148.5/1.001mhz 1.485/1.001gb/s high high high low 148.5mhz 540mb/s 1 high high high high 148.5/1.001mhz 540mb/s high high low low 148.5mhz 540mb/s 1 , 2 high high low high 148.5/1.001mhz 540mb/s 2 high low high low 148.5mhz 2.97gb/s high low high high 148.5/1.001mhz 2.97/1.001gb/s high low low low 148.5mhz 2.97gb/s 2 high low low high 148.5/1.001mhz 2.97/1.001gb/s 2 note: 1. for 720p30, 720p60, and 1080p30, the serial output rate when hd -vlc encoding is enabled will be 270x1.001mb/s. for 1080p60, t he encoded output rate will be 540x1.001mb/s. 2. for 3g 10-bit mode the clock is ddr
gv7700 final data sheet rev.7 pds-060377 december 2015 34 of 50 semtech www.semtech.com the use of a 27mhz or 54mhz crystal is supported, depending on the front-end isp chip reference clock frequency. xtal54_sel is an input pin which is set low when the default 27mhz crystal is used. the pin has an on-chip pull-down. when set high, a 54mhz crystal can be used. xtal_out is designed to driv e the front-end isp crystal in put pin. vddio_xout pin is the power supply for this buffer, which can be powered from 1.8v or 3.3v, depending on the isp requirement. while using the pclk as the frequency reference, set the input pin xtal_en high, connect the xtal pin to ground, and leave xtal pin floating. figure 4-17 shows a block diagram wi th the pclk, crystal co nnection and xtal_out back to isp chip. figure 4-17: external crystal frequency reference connection 4.11 serial data output the gv7700 has a single, low-impedance current mode differential output driver, capable of driving at least 800mv into a 75 single-ended load. the sdo and sdo pins of the device provid e the serial data output. compliance with all requirements defined in section 4.11.1 through section 4.11.2 is guaranteed when measured across a 75 terminated load at the output of 1m of belden 543945a cable, including the effects of the bnc and coaxial cable connection, except where otherwise stated. figure 4-18 illustrates this requirement. data xtal_out isp gv7700 pclk xtal xtal xtal_in xtal_en xtal54_sel 27mhz or 54mhz a39 a38 a22 a23 b14 a20 vddio_xout a19 1.8v or 3.3v
gv7700 final data sheet rev.7 pds-060377 december 2015 35 of 50 semtech www.semtech.com figure 4-18: bnc and coaxial cable connection 4.11.1 output signal interface levels the serial data output signals (sdo and sdo pins), of the device meet the amplitude requirements as defined in itu-r bt.656 and bt.1120 for an unbalanced generator (single-ended). these requirements are met across all ambient temperature and power supply operating conditions described in 2. electrical characteristics . 4.11.2 serial data output signal when the sdo_50_en pin is set high, the device outputs a 100 differential signal when the sdo_50_en pin is low, the serial data output signals of the device become 75 single-ended outputs, with both complementary outputs on by default. 4.12 gspi host interface the gv7700 is controlled via the gennum serial peripheral interface (gspi). the gspi host interface is comprised of a seri al data input signal (s din pin), serial data output signal (sdout pin), an active-low chip select (cs pin) and a burst clock (sclk pin). the gv7700 is a slave device, so the sclk, sdin, and cs signals must be sourced by the application host processor. all read and write access to the device is in itiated and terminated by the application host processor. 4.12.1 cs pin the chip select pin (cs ) is an active-low si gnal provided by the host processor to the gv7700. the high-to-low transition of this pin mark s the start of serial communication to the gv7700. the low-to-high transition of this pin mark s the end of serial communication to the gv7700. bnc 1m belden 543945a 75 coaxial cable 75 resistive load measuring device bnc coupling capacitor dut gv7700
gv7700 final data sheet rev.7 pds-060377 december 2015 36 of 50 semtech www.semtech.com 4.12.2 sdin pin the sdin pin is the gspi serial data input pin of the gv7700. the 16-bit command and data words from the host processor ar e shifted into the device on the rising edge of sclk when the cs pin is low. 4.12.3 sdout pin the sdout pin is the gspi serial data output of the gv7700. all data transfers out of th e gv7700 to the host processor occur from this pin. by default at power up or after system reset, the sdout pin provides a non-clocked path directly from the sdin pin, regardless of the cs pin state, except during the gspi data word portion for read op erations to the device. for read operations, the sdout pin is used to output data read from an internal configuration and status register (csr) when cs is low. data is shifted out of the device on the falling edge of sclk, so that it can be read by the host processor on the subsequent sclk rising edge. 4.12.4 sclk pin the sclk pin is the gspi serial data shift cl ock input to the device, and must be provided by the host processor. serial data is clocked into the gv7700 sdin pin on the rising edge of sclk. serial data is clocked out of the device fr om the sdout pin on the falling edge of sclk (read operation). sclk is ignored when cs is high. 4.12.5 command word description all gspi accesses are a minimum of 48 bits in length (a 16-bit command word, a 16-bit extended address field, and a 16-bit data wo rd) and the start of each access is indicated by the high-to-low transition of the chip select (cs ) pin of the gv7700. the format of the command word and data words are shown in figure 4-19 . data received immediately foll owing this high-to-low transi tion will be interpreted as a new command word. 4.12.5.1 r/ w bit - b15 command word this bit indicates a read or write operation. when r/w is set to 1, a read operation is indica ted, and data is read from the register specified by the address field of the command word. when r/w is set to 0, a write operation is indica ted, and data is written to the register specified by the address field of the command word.
gv7700 final data sheet rev.7 pds-060377 december 2015 37 of 50 semtech www.semtech.com 4.12.5.2 broadcast all - b14 command word this bit must always be set to 0. 4.12.5.3 emem - b13 command word this bit must always be set to 1. 4.12.5.4 autoinc - b12 command word when autoinc is set to 1, auto-increment read or write access is enabled. in auto-increment mode, the device automati cally increments the register address for each contiguous read or write access, starti ng from the address de fined in the address field of the command word. the internal address is incr emented for each 16-bit read or write access until a low-to-high transition on the cs pin is detected. when autoinc is set to 0, single read or write access is required. 4.12.5.5 unit address - b11:b5 command word the 7 bits of the unit address field of th e command word should always be set to 0. 4.12.5.6 address - b4:b0 command word , b15:b0 extended address the address word consists of bits [4:0] of the command word, plus another 16 bits [15:0] from the extended address word. the total command and data word format, including the extended address, is shown in figure 4-19 below. figure 4-19: command and data word format 4.12.6 data word description the data word portion of the gspi access cons ists of an 8-bit repe tition code, followed by an 8-bit read or write access payload. all registers in the gv7700 are 8 bits long, however since gspi write commands are required to be 16 bits long, the data word will have the same byte repeated. for example, to write fc h to a register within the csr, the 16-bit data word of the gspi command should be fcfc h . msb lsb 1 autoinc 0 0 0 00 command word unit address address[20:16] 0 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 data word r / w address[15:0] a16 a17 a18 a19 a20 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 repetition code payload (read/write data) 0 0
gv7700 final data sheet rev.7 pds-060377 december 2015 38 of 50 semtech www.semtech.com 4.12.7 gspi transaction timing figure 4-20: gspi exte rnal interface timing r/w 0 sclk write mode sdin signal is looped out on sdout sdout 1 a3 a2 a1 a0 r/w 0 sclk read mode sdin signal is looped out on sdout sdout 1 a3 a2 a1 a0 read data is output on sdout d0 r/w 0 sdin 1 0 0 0 0 0 a3 a2 a1 a0 d15 d14 d 13 d 12 d11 d10 d9 d8 r/w 0 sdin 1 auto_ inc a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d15 d 14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d15 d14 d13 d 12 d11 d10 d9 d8 t 0 t 8 t 2 t 3 t 1 t 9 t 6 t 5 t 7 t 4 sclk sdin command command data command command data sdout t cmd x x t 9 a14 a13 00000 a14 a13 00000 a14 a13 00000 a14 a13 32 sclk cycles 16 sclk cycles 32 sclk cycles 16 sclk cycles cs cs cs auto_ inc auto_ inc auto_ inc table 4-18: gspi timing parameters parameter symbol min typ max units cs low before sclk rising edge t 0 2.0 ns sclk frequency 45 mhz sclk period t 1 22.2 ns sclk duty cycle t 2 40 50 60 % input data setup time t 3 2.7 ns sclk idle time -write t 4 41.7 ns sclk idle time - read t 5 161.0 ns inter-command delay time t cmd 162.0 ns sdout after sclk falling edge t 6 7.5ns
gv7700 final data sheet rev.7 pds-060377 december 2015 39 of 50 semtech www.semtech.com 4.12.8 single read/write access single read/write access timing fo r the gspi interface is shown in figure 4-21 and figure 4-22 . when performing a single read or write access, one data word is read from/written to the device per access. each access is a mi nimum of 48-bits long, consisting of a command word, an extended address, and a single data word. the read or write cycle begins with a high-to-lo w transition of the cs pin. the read or write access is terminated by a low-to-high transition of the cs pin. the maximum interface clock frequency (sclk) is 45mhz and the inter-command delay time indicated in the figures as t cmd , is a minimum of 4 sclk clock cycles. for read access, the time from the last bit of the command word to the start of the data output, as defined by t 5 , corresponds to no less than 4 sclk clock cycles at 45mhz. figure 4-21: gspi write timing C single write access figure 4-22: gspi read timing C single read access cs high after final sclk falling edge t 7 0.0 ns input data hold time t 8 1.0 ns cs high time t 9 57.0 ns sdin to sdout combinational delay 5.0ns table 4-18: gspi timing parameters (continued) parameter symbol min typ max units sclk cs sdin sdout command [15:0] command [15:0] data [15:0] data [15:0] command [31:16] command [31:16] x x t cmd command [31:16] command [31:16] sclk cs sdin sdout command [15:0] command [15:0] data [15:0] t 5 command [31:16] command [31:16]
gv7700 final data sheet rev.7 pds-060377 december 2015 40 of 50 semtech www.semtech.com 4.12.9 auto-increment read/write access auto-increment read/write access timing for the gspi interface is shown in figure 4-23 and figure 4-24 . auto-increment mode is enab led by the setting of the autoinc bit of the command word. in this mode, multiple data words can be read from/written to th e device using only one starting address. each acce ss is initiated by a high-t o-low transition of the cs pin, and consists of a command word and one or more data words. the internal address is automatically incremen ted after the first read or writ e data word, and continues to increment until the read or write access is terminated by a low-to-high transition of the cs pin. the maximum interface clock frequency (sclk) is 45mhz and the inter-command delay time indicated in the diagram as t cmd , is a minimum of 4 sclk clock cycles. for read access, the time from the last bit of the first command word to the start of the data output of the first data word as defined by t 5 , will be no less than 4 sclk cycles at 45mhz. all subsequent read da ta accesses will not be subjec t to this delay during an auto-increment read. figure 4-23: gspi write timing C auto-increment figure 4-24: gspi read timing C auto-increment 4.13 jtag the gv7700 provides an ieee 1 149.1-compliant jtag tap in terface for bo undary scan test and debug. the gv7700 tap interface consists of the tck clock input, trst, tdi, and tms inputs, and the tdo output as defined in the standard. tms and tdi inputs are clocked with respect to the rising edge of tck and the tdo output with respect to the falling edge of tck. sclk cs sdin sdout command [15:0] command [15:0] data 1 data 1 data 2 data 2 command [31:16] command [31:16] sclk cs sdin sdout t 5 command [15:0] command [15:0] data 1 data 2 command [31:16] command [31:16]
gv7700 final data sheet rev.7 pds-060377 december 2015 41 of 50 semtech www.semtech.com 4.14 power supply and reset timing figure 4-25: power supply and reset timing note: configuration pins should be set prior to device reset. timing not critical vddio powering precedes vdd18_a vddio vdd18_a reset csr (control & status registers) t_resetb t_gspi_ready reset states csr accessible by gspi 1.8 C 3.3v 1.8v 1.8 C 3.3v t_resetb >= 10ms t_gspi_ready = 10s indeterminate states
gv7700 final data sheet rev.7 pds-060377 december 2015 42 of 50 semtech www.semtech.com 5. register map table 5-1: gv7700 regist er descriptions address register name parameter name bit slice r/w reset value description 486d h audio_sampling_ freq_reg audio_sampling_ freq 1:0 rw 0 audio sampling frequency. 00 = 48khz audio samples 01 = 44.1khz audio samples 10 = 32khz audio samples 486f h aud_ins_ctrl_reg mute_1_2 0:0 rw 0 audio mute for channels 1 & 2. when high, the device will insert audio samples with a value of 0 into channels 1 & 2. mute_3_4 1:1 rw 0 audio mute for channels 3 & 4. when high, the device will insert audio samples with a value of 0 into channels 3 & 4. 4879 h anc_ins_modes_reg anc_ins_enable 0:0 rw 0 enables ancillary data insertion. 1 = ancillary data insertion is enabled 0 = no ancillary data is inserted anc_ins_select 1:1 rw 0 mode allowing continuous insertion of the packet or only once. 1= packet inserted on current frame only 0 = continuous insertion on every frame 487a h anc_ins_line_number_ 10_8_reg anc_ins_line_ number_10_8 2:0 rw 0 defines line number for anc data insertion. bits 10 down to 8. 487b h anc_ins_line_number_ 7_0_reg anc_ins_line_ number_7_0 7:0 rw 0 defines line number for anc data insertion. bits 7 down to 0. 487c h anc_ins_number_ of_words_reg anc_ins_number_ of_words 4:0 rw 0 defines number of anc data words in the packet. includes: 000-3ff h -3ff h -did-sdid/dbn-dc-all udws-cs 487d h anc_ins_did_reg anc_ins_did 7:0 rw 0 did field of the ancillary data packet to be inserted. 487e h anc_ins_sdid_reg anc_ins_sdid 7:0 rw 0 sdid/dbn field of the anci llary data packet to be inserted. 487f h anc_ins_dc_reg anc_ins_dc 7:0 rw 0 dc field of the ancillary data packet to be inserted. 4880 h anc_ins_udw0_reg anc_ins_udw0 7:0 rw 0 user data word 0 of the ancillary data packet to be inserted. 4881 h anc_ins_udw1_reg anc_ins_udw1 7:0 rw 0 user data word 1 of the ancillary data packet to be inserted. 4882 h anc_ins_udw2_reg anc_ins_udw2 7:0 rw 0 user data word 2 of the ancillary data packet to be inserted.
gv7700 final data sheet rev.7 pds-060377 december 2015 43 of 50 semtech www.semtech.com 4883 h anc_ins_udw3_reg anc_ins_udw3 7:0 rw 0 user data word 3 of the ancillary data packet to be inserted. 4884 h anc_ins_udw4_reg anc_ins_udw4 7:0 rw 0 user data word 4 of the ancillary data packet to be inserted. 4885 h anc_ins_udw5_reg anc_ins_udw5 7:0 rw 0 user data word 5 of the ancillary data packet to be inserted. 4886 h anc_ins_udw6_reg anc_ins_udw6 7:0 rw 0 user data word 6 of the ancillary data packet to be inserted. 4887 h anc_ins_udw7_reg anc_ins_udw7 7:0 rw 0 user data word 7 of the ancillary data packet to be inserted. 4888 h anc_ins_udw8_reg anc_ins_udw8 7:0 rw 0 user data word 8 of the ancillary data packet to be inserted. 4889 h anc_ins_udw9_reg anc_ins_udw9 7:0 rw 0 user data word 9 of the ancillary data packet to be inserted. 488a h anc_ins_udw10_reg anc_ins_udw10 7:0 rw 0 user data word 10 of the ancillary data packet to be inserted. 488b h anc_ins_udw11_reg anc_ins_udw11 7:0 rw 0 user data word 11 of the ancillary data packet to be inserted. 488c h anc_ins_udw12_reg anc_ins_udw12 7:0 rw 0 user data word 12 of the ancillary data packet to be inserted. 488d h anc_ins_udw13_reg anc_ins_udw13 7:0 rw 0 user data word 13 of the ancillary data packet to be inserted. 488e h anc_ins_udw14_reg anc_ins_udw14 7:0 rw 0 user data word 14 of the ancillary data packet to be inserted. 488f h anc_ins_udw15_reg anc_ins_udw15 7:0 rw 0 user data word 15 of the ancillary data packet to be inserted. 4891 h tpg_ctrl_reg insert_test_ pat_enable 0:0 rw 0 enables the test pattern insertion on the active picture region of the incoming video data. 1 = enables the insertion of the test patterns 0 = no insertion pat tern_sel 1:1 r w 0 test pattern selection. 0 = pathological test pattern 1 = flat-field test pattern 4894 h tpg_patho_pll_line_ f1_10_8_reg patho_pll_line_ f1_10_8 2:0 rw 0 starting line number for the pathological pll testing when fin = 0. bits 10 down to 8. 4895 h tpg_patho_pll_line_ f1_7_0_reg patho_pll_line_ f1_7_0 7:0 rw 0 starting line number for the pathological pll testing when fin = 0. bits 7 down to 0. 4896 h tpg_patho_pll_line_ f2_10_8_reg patho_pll_line_ f2_10_8 2:0 rw 0 starting line number for the pathological pll testing when fin = 1. bits 10 down to 8. table 5-1: gv7700 register de scriptions (continued) address register name parameter name bit slice r/w reset value description
gv7700 final data sheet rev.7 pds-060377 december 2015 44 of 50 semtech www.semtech.com 4897 h tpg_patho_pll_line_ f2_7_0_reg patho_pll_line_ f2_7_0 7:0 rw 0 starting line number for the pathological pll testing when fin = 1. bits 7 down to 0. 4898 h tpg_pixel0_cb0_9_8_ reg pixel0_cb0_9_8 1:0 rw 0 pixel 0 setting register. cb0. bits 9 down to 8. 4899 h tpg_pixel0_cb0_7_0_ reg pixel0_cb0_7_0 7:0 rw 0 pixel 0 setting register. cb0. bits 7 down to 0. 489a h tpg_pixel0_y0_9_8_ reg pixel0_y0_9_8 1:0 rw 0 pixel 0 setting register. y0. bits 9 down to 8. 489b h tpg_pixel0_y0_7_0_ reg pixel0_y0_7_0 7:0 rw 0 pixel 0 setting register. y0. bits 7 down to 0. 489c h tpg_pixel0_cr0_9_8_ reg pixel0_cr0_9_8 1:0 rw 0 pixel 0 setting register. cr0. bits 9 down to 8. 489d h tpg_pixel0_cr0_7_0_ reg pixel0_cr0_7_0 7:0 rw 0 pixel 0 setting register. cr0. bits 7 down to 0. 489e h tpg_pixel0_y1_9_8_ reg pixel0_y1_9_8 1:0 rw 0 pixel 0 setting register. y1. bits 9 down to 8. 489f h tpg_pixel0_y1_7_0_ reg pixel0_y1_7_0 7:0 rw 0 pixel 0 setting register. y1. bits 7 down to 0. 48a0 h tpg_pixel1_cb0_9_8_ reg pixel1_cb0_9_8 1:0 rw 0 pixel 1 setting register. cb0. bits 9 down to 8. 48a1 h tpg_pixel1_cb0_7_0_ reg pixel1_cb0_7_0 7:0 rw 0 pixel 1 setting register. cb0. bits 7 down to 0. 48a2 h tpg_pixel1_y0_9_8_ reg pixel1_y0_9_8 1:0 rw 0 pixel 1 setting register. y0. bits 9 down to 8. 48a3 h tpg_pixel1_y0_7_0_ reg pixel1_y0_7_0 7:0 rw 0 pixel 1 setting register. y0. bits 7 down to 0. 48a4 h tpg_pixel1_cr0_9_8_ reg pixel1_cr0_9_8 1:0 rw 0 pixel 1 setting register. cr0. bits 9 down to 8. 48a5 h tpg_pixel1_cr0_7_0_ reg pixel1_cr0_7_0 7:0 rw 0 pixel 1 setting register. cr0. bits 7 down to 0. 48a6 h tpg_pixel1_y1_9_8_ reg pixel1_y1_9_8 1:0 rw 0 pixel 1 setting register. y1. bits 9 down to 8. 48a7 h tpg_pixel1_y1_7_0_ reg pixel1_y1_7_0 7:0 rw 0 pixel 1 setting register. y1. bits 7 down to 0. 48a8 h crc_ins_enable_reg crc_ins_enable 0:0 rw 0 when high, enables the crc insertion. when low, crc insertion will not be done. must be set high when tpg mode enabled. table 5-1: gv7700 register de scriptions (continued) address register name parameter name bit slice r/w reset value description
gv7700 final data sheet rev.7 pds-060377 december 2015 45 of 50 semtech www.semtech.com 6. typical application circuit figure 6-1: gv7700 typical application circuit yc_din19 yc_din18 yc_din17 yc_din16 yc_din15 yc_din14 yc_din13 yc_din12 yc_din11 yc_din10 yc_din8 yc_din7 yc_din6 yc_din5 yc_din4 yc_din3 yc_din2 yc_din1 yc_din0 field pclk vblank hblank sys_rst spi_cs_gv7700 spi_sdin_gv7700 spi_clk_gv7700 spi_dout_gv7700 sdo_50_en audio_en yc_din9 vdd_io gnd vdd_io vdd_io gnd gnd vdd_io vdd_1v8a gnd gnd gnd gnd gnd 4.7f 470nf 470nf 18pf nc nc 4.7f ucbbje20-1 1 3 2 4 5 100k 27mhz 1 2 3 4 470nf 470nf 470nf gv7700 din_0 a15 din_1 b10 din_2 a14 din_3 a13 din_4 a12 din_5 a11 din_6 b9 din_7 a10 din_8 a9 din_9 b7 din_10 a8 din_11 b6 din_12 a7 din_13 b5 din_14 a6 din_15 a5 din_16 b3 din_17 a4 din_18 b2 din_19 a3 fin a16 hin a17 vin b12 rsvd a1 sdo_50_en a2 rsvd b1 vddio b4 vddio b11 n/c b13 vddio a18 b19 n/c b15 xtal_out a20 cap1 b16 vdd18_a a21 cap2 b17 cap3 b18 xtal a22 a23 vdd18_a a24 rbias a25 vdd18_a a26 vddio_xout a19 sdo a28 a27 vdd18_a a29 vdd18_a b22 cap5 a30 cap4 b23 rsvd a31 vddio b24 rsvd rsvd a32 tdi b25 rsvd a33 trst b26 tms a34 tdo b27 tck a35 vddio a36 vddio a37 a39 hdvlc_en hdvlc_en b29 ain_3_4 a40 ain_1_2 b30 aclk a41 audio_en b31 wclk a42 vddio b32 div_1001 div_1001 a43 detect_trs detect_trs b33 a44 b34 bit20_10 a45 b35 sdin a46 vddio b36 sclk a47 sdout a48 center pad tab xtal54_sel a38 vddio b8 rsvd b28 pclk b14 18pf 11k 1f dnp 10k 10k 0 vdd_io 10k cs gnd 75 sdo bit20_bit10 xtal reset xtal_en b20 b21 vdd18_a vdd18_a vdd18_a to isp vdd_io vdd_io threeg_hd threeg_hd
gv7700 final data sheet rev.7 pds-060377 december 2015 46 of 50 semtech www.semtech.com figure 6-2: alternative catx output circuit 6.1 power supply decoupling and filtering figure 6-3: gv7700 power supply decoupling and filtering schematic gv7700 sdo sdon a28 a27 1 2 5 3 4 6 7 8 reserved for power reserved for ucc 1f 1f rj45 white/orange white/green blue green white/blue white/brown brown orange vdd_io gnd gnd gnd vdd_1v8a 10nf 10nf 10nf 1f 10nf 10nf 10nf 10nf 10nf 10nf 10nf 10nf 10nf 10nf 10nf 1f 10nf 10nf 10nf 10nf 1.8v or 3.3v
gv7700 final data sheet rev.7 pds-060377 december 2015 47 of 50 semtech www.semtech.com 7. packaging information 7.1 package dimensions figure 7-1: gv7700 package dimensions 7.00 7.00 a b c 0.15 ref 0.10 c 0.08 c 84x s eating plane 0.850.10 0.02 C0.02 +0.03 pin 1 area 0.15 c 0.15 c 2x 2x a37 a3 6 b28 b27 a25 a24 b19 b18 a12 a13 b9 b10 a48 a1 b3 6 b1 datum b detail b datum a 2.800.10 0.10 c ab m 0.10 c ab m 2.800.10 0.10 c ab m 0.05 c 0.220.05 84x outer terminal tip 0.10 c ab m 0.400.10 84x 0.50 / 2 0.50 0. 6 5 0.400.10 0.50 datum a inner terminal tip detail b ( sc ale 3:1) note s : 1. dimen s ioning and toleran c e i s in c onforman c e to a s me y14.5C1994 all dimen s ion s are in millimeter s in degree s 2. dimen s ion of lead width applie s to metallized terminal and i s mea s ured between 0.15mm and 0.30mm from the terminal tip (both row s ). if the terminal ha s optional radiu s on the end of the terminal, the lead width dimen s ion s hould not be mea s ured in that radiu s area
gv7700 final data sheet rev.7 pds-060377 december 2015 48 of 50 semtech www.semtech.com 7.2 recommended pcb footprint figure 7-2: gv7700 pcb footprint 7.3 marking diagram figure 7-3: gv7700 marking diagram center pad notes: 1. all dimensions in millimeters 2. all signal pads have a 0.11mm inner end radius 2.8 5.3 6 .7 0.4 0.22 0.22 0. 6 0.5 0.5 gv7700 xxxxe3 yyww pin 1 id xxxx - last 4 digits of assembly lot e3 - pb-free & green indicator yyww - date code
gv7700 final data sheet rev.7 pds-060377 december 2015 49 of 50 semtech www.semtech.com 7.4 solder reflow profile figure 7-4: maximum pb-free solder reflow profile 7.5 packaging data 7.6 ordering information 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max table 7-1 gv7700 pacaging data parameter value package type/dimensions/pad pitch dual-row qfn: 84l 7mm x 7mm, 0.5mm pitch moisture sensitivity level (msl) 3 junction to case thermal resistance, j-c 28.8c/w junction to ambient thermal resistance (zero airflow), j-a 42c/w junction-to-top of package characterization, j-t 1.0c/w junction to board thermal resistance, j-b 13.6c/w pb-free and rohs compliant yes table 7-2: gv7700 ordering information part package GV7700-INE3 84-pin dual-row qfn (260 pc/tray)
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